RoHS Compliant 100GB/S Qsfp28 Sr4 100m Optical SFP Transceiver

Modello numero.
GFC-OLSQ85TXM-CDS1

Tempi di consegna
3-7 Giorni

Modello
Qsfp

Garanzia
2 Years

Distance
100M

Pacchetto di trasporto
Antistatic Bag

Specifica
100G

Marchio
GFC

Origine
Cina

Codice HS
8517706000

Capacità produttiva
50K/Month

Descrizione

Caratteristiche del prodotto
MTP/MP0 optical connector
Single +3.3V power supply
Hot-pluggable QSFP28 MSA form factor
Up to 100m OM4 MMF Distance
4x28G Electrical Serial Interface (CEI-28G-VSR)
AC coupling of CML signals
Low power dissipation(Massimo:3.5W)
Built in digital diagnostic function
Operating case temperature range:0ºC A 70ºC
Compliant with 100GBASE-SR4
I2C Communication Interface
Applicazioni
100GBASE-SR4
Infiniband QDR/DDR/SDR
100G Datacom connections

Standards
Compliant with IEEE 802.3ba
Compliant with QSFP28 MSA hardware specifications
Compliant with RoHS
Functional Description
The 100G QSFP28 SR4 optical transceiver integrates the transmit and receive path onto one module. It
converts parallel electrical input signals into parallel optical signals, by a driven Vertical Cavity Surface Emitting
Laser (VCSEL) array. The transmitter module accepts electrical input signals compatible with Common Mode
Logic (CML) levels. All input data signals are differential and internally terminated. The receiver module converts
parallel optical input signals via a photo detector array into parallel electrical output signals. The reCML) levels.
All data signals are differential and support a data rates up to 27.9525Gb/s per channel.ceiver module outputs
electrical signals are also voltage compatible with Common Mode LogicOn This module features a hot-pluggable
electrical interface, low power consumption, and 2-wire serial interface.

Absolute Maximum Ratings

Parametro Symbol minimo. Massimo. Unit Note
Supply Voltage Vcc -0.5 3.6 V
Storage Temperature TS -40 85 °C
Relative Humidity RH 0 85 %
Rx Damage Threshold,per Lane PRdmg 5.5 dBm

Note: Stress in excess of the maximum absolute ratings can cause permanent damage to the transceiver.

Recommended Operating Conditions

Parametro Symbol minimo Typ Massimo Units Note
Operating Case Temperature TC 0 +70 °C
Power Supply Voltage VCC 3.14 3.3 3.47 V
Data rate 103.125 112 Gb/s
Link Distance (OM3) 70 M
Link Distance (OM4) 100 M

Electrical Characteristics (Top=0~70ºC, Vcc=3.14~3.47V)

(Tested under recommended operating conditions,unless otherwise noted)

Parametro Symbol minimo Typ Massimo Unit Note
Transmitter
Signaling rate per lane DRPL 25.78125 ± 100 ppm Gb/s
Differential pk-pk input voltage tolerance Vin,dpp 900 mV
Single-ended voltage tolerance Vin,pp -0.35 +3.3 V
Module stress input test Per IEEE 802.3bm
Receiver
Signaling rate per lane DRPL 25.78125 ± 100 ppm Gb/s
Differential data output swing Vout,pp 400 800 mV
Eye width Ew 0.57 UI
Vertical eye closure VEC 5.5 dB
Differential termination mismatch TM 10 %
Transition time, 20% A 80% Tr,Tf 12 ps

Optical Characteristics (Top=0~70ºC, Vcc=3.14~3.47V)

(Tested under recommended operating conditions,unless otherwise noted)

Parametro Symbol Unit minimo Typ Massimo Note
Transmitter
Signaling rate, each lane DRpl Gb/s 25.78125 ±100 ppm 1
Center Wavelengthe λ nm 840 850 860
RMS Spectral Width nm 0.6
Average launch power, each lane Pavg dBm -8.4 2.4
Optical modulation amplitude, each lane (OMA) OMA dBm -6.4 3
Extinction ratio ER dB 2
Average Launch Power of OFF Transmitter, per Lane RIN dBm -30
Encircled Flux FLX dBm >86% at 19 uno

<30% at 4.5 uno
Optical return loss tolerance dB 12
Transmitter eye mask {X1, X2, X3, Y1, Y2, Y3} {0.3,0.38,0.45,0.35,0.41,0.5} 2
Receiver
Receive Rate for Each Lane DRpl Gb/s 25.78125 ±100 ppm 3
Four Lane Wavelength Range λ nm 840 860
Overload Input Optical Power Pmax dBm 3.4
Average Receive Power for Each Lane Spillo dBm -10.3 2.4 4
Receiver Sensitivity(OMA)per lane Psens dBm -5.2
Recevier Reflectance Rfl dB -12
Receiver Eye MaskDefinition {X1, X2, X3, Y1, Y2,Y3} {0.28,0.5,0.5,0.33,0.33,0.4} 5
Los De-Assert Pd dBm -13
Los Assert Pa dBm -30
Loss Hysteresis Pd-Pa dBm 0.5

Note:

  1. Transmitter consists of 4 lasers operating at a maximum speed of 25.78125Gb/s ±100ppm each.
  2. Hit Ratio 1.5 x 10-3 hits/sample.
  3. Receiver consists of 4 photodetectors operating at a maximum speed of 25.78125Gb/s ±100ppm each.
  4. Minimum value is informative only E not the principal indicator of signal strength.
  5. Hit Ratio 5 x 10-5 hits/samples

Spillo Nome Logic Descrizione
1 GND Ground 1
2 Tx2n CML-I Transmitter Inverted Data Input 10
3 Tx2p CML-I Transmitter Non-Inverted Data Input 10
4 GND Ground 1
5 Tx4n CML-I Transmitter Inverted Data Input 10
6 Tx4p CML-I Transmitter Non-Inverted Data Input 10

7 GND Ground 1
8 ModSelL LVTTL-I Module Select 3
9 ResetL LVTTL-I Module Reset 4
10 Vcc Rx +3.3V Power Supply Receiver 2
11 SCL LVCMOS 2-wire serial interface clock 5
12 SDA LVCMOS 2-wire serial interface data 5
13 GND Ground 1
14 Rx3p CML-O Receiver Non-Inverted Data Output 9
15 Rx3n CML-O Receiver Inverted Data Output 9
16 GND Ground 1
17 Rx1p CML-O Receiver Non-Inverted Data Output 9
18 Rx1n CML-O Receiver Inverted Data Output 9
19 GND Ground 1
20 GND Ground 1
21 Rx2n CML-O Receiver Inverted Data Output 9
22 Rx2p CML-O Receiver Non-Inverted Data Output 9
23 GND Ground 1
24 Rx4n CML-O Receiver Inverted Data Output 9
25 Rx4p CML-O Receiver Non-Inverted Data Output 9
26 GND Ground 1
27 ModPrsL LVTTL-O Module Present 6
28 IntL LVTTL-O Interrupt 7
29 Vcc Tx +3.3V Power supply transmitter 2
30 Vcc1 +3.3V Power supply 2
31 LPMode LVTTL-I Low Power Mode 8
32 GND Ground 1
33 Tx3p CML-I Transmitter Non-Inverted Data Input 10
34 Tx3n CML-I Transmitter Inverted Data Input 10
35 GND Ground 1
36 Tx1p CML-I Transmitter Non-Inverted Data
37 Tx1n CML-I Transmitter Inverted Data Input 10
38 GND Ground 1

Note:

1: GND is the symbol for signal and supply (power) common for the module. All are common within the module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common ground plane.

2: Vcc Rx, Vcc1 and Vcc Tx shall be applied concurrently. Vcc Rx Vcc1 and Vcc Tx may be internally connected within the module in any combination. The connector pins are each rated for a maximum current of 1000 mA. Recommended host board power supply filtering is shown below .

3: The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple modules on a single 2-wire interface bus. When the ModSelL isHigh”, the module shall not respond to or acknowledge any
2-wire interface communication from the host. ModSelL signal input node shall be biased to the High state in the module. In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any modules are deselected. Similarly, the host shall wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.
4: The ResetL pin shall be pulled to Vcc in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by assertinglowan IntL signal with the Data_Not_Ready bit negated.
Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

5: Low speed signaling other than SCL and SDA is based on Low Voltage TTL (LVTTL) operating at Vcc. Vcc refers to the generic supply voltages of VccTx, VccRx, Vcc_host or Vcc1.
Hosts shall use a pull-up resistor connected to Vcc_host on each of the 2-wire interface SCL (clock), SDA (data), and all low speed status outputs. The SCL and SDA is a hot plug interface that may support a bus topology.

6: ModPrsL is pulled up to Vcc_Host on the host board and grounded in the module. The ModPrsL is assertedLowwhen inserted and deassertedHighwhen the module is physically absent from the host connector.
7: IntL is an output pin. When IntL isLow”, it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and shall be pulled to host supply voltage on the host board. The INTL pin is deassertedHighafter completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of ‘0’ and the flag field is read (see SFF-8636).
8: The LPMode pin shall be pulled up to Vcc in the module. The pin is a hardware control

used to put modules into a low power mode when high. By using the LPMode pin and a combination of the Power_override, Power_set and High_Power_Class_Enable software control bits (Address A0h, byte 93 bits 0,1,2), the host controls how much power a module can dissipate.

9: Rx(n)(p/n) are module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm differential lines that should be terminated with 100 Ohm differentially at the Host ASIC(SerDes). The AC coupling is inside the module and not required on the Host board. For operation at 28 Gb/s the relevant standards (e.g., OIF CEI v3.1) define the signal requirements on the high-speed differential lines. For operation at lower rates, refer to the relevant standards.
Note: Due to the possibility of insertion of legacy QSFP and QSFP+ modules into a host

designed for higher speed operation, it is recommended that the damage threshold of the host input be at least 1600 mV peak to peak differential. Output squelch for loss of optical input signal, hereafter Rx Squelch, is required and shall function as follows. In the event of the optical signal on any channel becoming equal to or less than the level required to assert LOS, then the receiver data output for that channel shall be squelched or disabled. In the squelched or disabled state output impedance levels are maintained while the differential voltage swing shall be less than 50 mVpp. In normal operation the default case has Rx Squelch active. Rx Squelch can be deactivated using Rx Squelch Disable through the 2-wire serial interface. Rx Squelch Disable is an optional function. For specific details refer to SFF-8636.
10: Tx(n)(p/n) are module transmitter data inputs. They are AC-coupled 100 Ohm differential lines with 100 Ohm differential terminations inside the module. The AC coupling is inside the module and not required on the Host board. For operation at 28 Gb/s the relevant standards (e.g., OIF CEI v3.1) define the signal requirements on the high-speed differential lines. For operation at lower rates, refer to the relevant standards. Due to the possibility of insertion of modules into a host designed for lower speed operation, the damage threshold of the module input shall be at least 1600 mV peak A peak differential. Produzione squelch, hereafter Tx Squelch, for loss of input signal, hereafter Tx LOS, is an optional function. Where implemented it shall function as follows. In the event of the differential, peak-to-peak electrical signal on any channel becomes less than 50 mVpp, then the transmitter optical output for that channel shall be squelched or disabled and the associated TxLOS flag set. Where squelched, the transmitter OMA shall be less than or equal to -26 dBm and when disabled the transmitter power shall be less than or equal to -30 dBm. For applications, e.g. Ethernet, where the transmitter off condition is defined in terms of average power, disabling the transmitter is recommended and for applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of OMA, squelching the transmitter is recommended. In module operation, where Tx Squelch is implemented, the default case has Tx Squelch active. Tx Squelch can be deactivated using Tx Squelch Disable through the 2-wire serial interface. Tx Squelch Disable is an optional function. For specific details refer to SFF- 8636.

Lane Assignment

Fiber Lane
1 RX0
2 RX1
3 RX2
4 RX3
5678 Not used
9 TX3
10 TX2
11 TX1
12 TX0

Ordering Information

Part Number Descrizione
GFC-OLSQ85TXM-CDS1 QSFP28 SR4 100m OM4, 0~70ºC, with Digital Diagnostic Monitor

RoHS Compliant 100GB/S Qsfp28 Sr4 100m Optical SFP Transceiver
RoHS Compliant 100GB/S Qsfp28 Sr4 100m Optical SFP Transceiver